This invention relates to data communication systems, and more particularly, to an architecture and method of operating dequeuing logic of a multiport communication switch.
A multiport communication switch may be provided in a data communication network to enable data communication between multiple network stations connected to various ports of the switch. A logical connection may be created between receive ports and transmit ports of the switch to forward received data packets, e.g., frame data, to appropriate destinations. Based on frame headers, a frame forwarding arrangement selectively transfers received frame data (packet data) to a destination station.
Data packets received at a receive port of the communication switch are transferred to an external memory and subsequently retrieved and transferred to a transmit queue for transmission from a respective transmit port of the switch. Dequeuing logic corresponding to each transmit port is responsible for transferring frame data from the external memory to the respective transmit queue of the corresponding transmit port. Conventional architecture and operation of the dequeuing logic do not fully utilize the bandwidth of the external memory which results in a dequeuing process which is relatively slow, decreasing operational performance of the switch. Thus, there is a need to provide architecture and operation of the dequeuing logic which fully utilizes the bandwidth of the external memory in order to speed up the dequeuing process and increase operational performance of the switch.
The invention provides a novel multiport data communication system for switching data packets between ports and comprises a plurality of receive ports for receiving data packets, a memory storing the received data packets, a plurality of transmit ports for transmitting data packets, each transmit port having a transmit queue storing data packets to be transmitted from the respective port, a plurality of queues, each corresponding to a respective transmit port and storing indicators of where the data packets are stored in the memory, and a plurality of logic circuitry corresponding to the plurality of transmit ports. Each logic circuitry performs each of the operations of reading respective frame pointers from the plurality of queues, reading the respective data packets corresponding to the respective frame pointers from the memory, and writing each read data packet to the corresponding transmit queue in a pipeline manner.
The invention provides also, in a multiport data communication system having a plurality of receive ports for receiving data packets, a memory storing the received data packets, a plurality of transmit ports for transmitting data packets, each transmit port having a transmit queue storing data packets to be transmitted from the respective port, a plurality of queues, each corresponding to a respective transmit port and storing indicators of where the data packets are stored in the memory, and a plurality of logic circuitry corresponding to the plurality of transmit ports, a method of operating each logic circuitry comprising reading respective frame pointers from the plurality of queues, reading the respective data packets corresponding to the respective frame pointers from the memory, and writing each read data packet to the corresponding transmit queue, all carried out in a pipeline manner.